FPGA Acceleration of AES Algorithm for High-Performance Cryptographic Applications

https://doi.org/10.55529/ijitc.44.1.11

Authors

  • Abdullah Farhan Siddiqui Student, Department of Electronics and Communication Engineering, Osmania University, Hyderabad, India
  • Prof. P. Chandra Sekhar Professor, Department of Electronics and Communication Engineering, Osmania University, Hyderabad, India.

Keywords:

Field Programmable Gate Array, Advanced Encryption Standard, Look up Table.

Abstract

This research paper presents the FPGA implementation of the AES-128 Algorithm as an accelerator tailored for high-performance cryptographic applications. Leveraging the capabilities of the Virtex-7 evaluation kit, the AES algorithm is meticulously coded using Xilinx Vivado software. The results of the implementation reveal a resource-efficient design, utilizing 588 Look-Up Tables (LUTs) and 353 Flip Flops. This implementation showcases the efficacy of FPGA technology, specifically the Virtex-7 device, in achieving a fine balance between algorithmic complexity and resource utilization for cryptographic acceleration. The abstract underscores the significance of this research in advancing the field of hardware-accelerated cryptographic applications, offering a scalable solution with promising resource efficiency on the FPGA platform.

Published

2024-06-03

How to Cite

Abdullah Farhan Siddiqui, & Prof. P. Chandra Sekhar. (2024). FPGA Acceleration of AES Algorithm for High-Performance Cryptographic Applications . International Journal of Information Technology & Computer Engineering , 4(4), 1–11. https://doi.org/10.55529/ijitc.44.1.11

Issue

Section

Aricle Publication

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